Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication
نویسندگان
چکیده
منابع مشابه
A New Floating Point Arithmetic with Error Tracking Capability
A new modeless floating-point arithmetic called the precision arithmetic is developed to track, limit, and reject the accumulation of calculation errors during floating point calculations, by reinterpreting the polymorphic representation of the conventional floating point arithmetic. The validity of this strategy is demonstrated by tracking the calculation errors and by rejecting the meaningles...
متن کاملImproved Floating-Point Matrix Multiplier
* This work is partially supported by NSC 99-2221-E-260-010-. † Correspondence to: D.-R. Duh; E-mail address: [email protected] Abstract – Floating-point matrix multiplier is widely used in scientific computations. A great deal of efforts has been made to achieve higher performance. The matrix multiplication consists of many multiplications and accumulations. Yang and Duh proposed a modular des...
متن کاملNULL Convention Floating Point Multiplier
Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The ...
متن کاملA Single Precision Asynchronous Floating Point Multiplier
This paper presents the delay of carry save based multiplier of 65nm technology using Field Programmable Gate Array is in enable mode. Here we present a design of floating point multiplication and that can utilize the decimal carry save addition is reduce path delay and dissipation power. The multiplier can stores a less number of multiplicand uses a decimal carry save addition in the portion o...
متن کاملA dual precision IEEE floating-point multiplier
We present a design of an IEEE oating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the la-tency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fteen logic levels. A single-precision multiplication can be followed immediately by a...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEICE Transactions on Information and Systems
سال: 2017
ISSN: 0916-8532,1745-1361
DOI: 10.1587/transinf.2016edp7158